Live free or die hard: Design for reliability in 3D integrated circuits

Yu Guang Chen, Yiyu Shi, Shih Chieh Chang

Research output: Chapter in Book/Report/Conference proceedingChapterpeer-review


In this chapter, we discuss the reliability issues about 3D-ICs fabrication process under technologies nowadays, and propose possible solutions to address the problems. In Section 9.1, we lay down the reasons in detail as to why there are seldom 3D-IC products today versus the problem of low yield of TSVs. Section 9.2 shows two major fault-tolerant structures, double TSV and shared-spare TSV, to improve the chip yield. The fault-tolerant design constraints then are addressed in Section 9.3. In Section 9.4, we address the problem of spare TSV assignment, and proposed two heuristics to optimize area overhead under given constraints. A fault-tolerance clock network then is discussed in Section 9.5 with two different structures. Concluding remarks are given in Section 9.6.

Original languageEnglish
Title of host publicationPhysical Design for 3D Integrated Circuits
PublisherCRC Press
Number of pages35
ISBN (Electronic)9781498710374
ISBN (Print)9781498710367
StatePublished - 1 Jan 2017


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