An ATPG (automatic test pattern generation) system that consists of three optional test pattern generators and a fault simulator is presented. The three test pattern generators include a random pattern generator with the linear feedback shift register (LFSR) technique, a pseudorandom pattern generator, DISRUPT, and a deterministic test pattern generator, SLOPE1, which employs dynamic compaction to increase the fault coverage. The generators, together with a fault simulator, ACCEPT, generate test sets much smaller than those reported for other ATG systems while achieving the same or even better fault coverage with comparable system run times.
|Number of pages||3|
|State||Published - 1989|
|Event||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers - Taipei, Taiwan|
Duration: 17 May 1989 → 19 May 1989
|Conference||International Symposium on VLSI Technology, Systems and Applications - Proceedings of Technical Papers|
|Period||17/05/89 → 19/05/89|