Layout techniques for on-chip interconnect inductance reduction

Shang Wei Tu, Jing Yang Jou, Yao Wen Chang

Research output: Contribution to conferencePaperpeer-review

1 Scopus citations

Abstract

As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques - ground-aware net routing and source pin positioning - that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.

Original languageEnglish
Pages269-273
Number of pages5
StatePublished - 2004
EventProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan
Duration: 27 Jan 200430 Jan 2004

Conference

ConferenceProceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004
Country/TerritoryJapan
CityYokohama
Period27/01/0430/01/04

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