Abstract
As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Some of the previous techniques such as net ordering, shield insertion, twisted-bundle layout structure, and interdigitated techniques are either inefficient or incur too much area penalty. In this paper, we present two techniques - ground-aware net routing and source pin positioning - that can reduce inductance effectively without incurring area penalty. In order to prove the effectiveness of our techniques, we use the famous 3D field-solver FastHenry to extract inductances and verify our results. All simulation results show that our proposed techniques can significantly reduce inductances without incurring area penalty.
Original language | English |
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Pages | 269-273 |
Number of pages | 5 |
State | Published - 2004 |
Event | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 - Yokohama, Japan Duration: 27 Jan 2004 → 30 Jan 2004 |
Conference
Conference | Proceedings of the ASP - DAC 2004 Asia and South Pacific Design Automation Conference - 2004 |
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Country/Territory | Japan |
City | Yokohama |
Period | 27/01/04 → 30/01/04 |