Latched CMOS Differential Logic (LCDL) for Complex High-Speed VLSI

Chung Yu Wu, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

14 Scopus citations


A new CMOS differential logic, called the latched CMOS differential logic (LCDL), is proposed and analyzed. LCDL circuits can implement a complex combinational logic function in a single gate, and form the pipeline structure as well. It is shown that the LCDL with a fan-in number between 6 and 15 has the highest operation speed among those differential logic circuits. It is also free from charge-sharing, clock-skew, and race problems. Experimental results have verified the high speed and race-free performance of the proposed LCDL.

Original languageEnglish
Pages (from-to)1324-1328
Number of pages5
JournalIEEE Journal of Solid-State Circuits
Issue number9
StatePublished - Sep 1991


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