Large or Small: Harnessing the Erase Duality of Emerging Bit-Alterable NAND Flash to Suppress Tail Latency

  • Guangliang Yao
  • , Tsun Yu Yang
  • , Yingjia Wang
  • , Tseng Yi Chen
  • , Ming Chang Yang

Research output: Contribution to journalArticlepeer-review

Abstract

High-density NAND flash has revolutionized the storage ecosystem because of its rapidly decreasing per-bit costs and unprecedented capacities. However, the inherent large block size of modern high-density NAND flash inevitably aggravates the reclamation latency (i.e., the time required to reclaim the storage space occupied by the obsolete data), which subsequently prolongs the tail latency of flash-based storage devices. Inspired by the “erase duality” from the emerging bit-alterable NAND flash, this article proposes a reclamation latency suppressed (RLS) space management design to synergize the strengths of both block-level erase and page-level erase. Taking into account the data update frequency during runtime, RLS enables proactive adjustment of the dual-granularity erase. Moreover, RLS tightly couples the data cluster allocation strategy with a novel dual-granularity space reclamation design, thereby alleviating the reclamation latency. We extensively examine the benefits of RLS with real-world workloads. Our evaluation results reveal that, with the suppressed space reclamation latency, RLS achieves up to 37.51% improvement for both write and read tail latency (latency at the 99.9th percentile) compared with the state-of-the-art approaches.

Original languageEnglish
Article number98
JournalACM Transactions on Embedded Computing Systems
Volume24
Issue number5 s
DOIs
StatePublished - 30 Sep 2025

Keywords

  • Bit-alterable NAND Flash
  • Data Update Frequency
  • Erase Duality
  • Reclamation Latency
  • Tail Latency

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