JPEG2000 encoder architecture design with Fast EBCOT algorithm

Tsung Han Tsai, Lian Tsung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

This paper presents an architecture design for JPEG2000 with a fast algorithm in EBCOT. The EBCOT algorithm takes advantages of resolution and SNR scalability together with a random access property, but its complexity also becomes the bottleneck of JPEG2000. In this paper, we propose fast algorithm that using two speed-up methods for EDCOT context modeling. The gate counts of JPEG2000 design is about 105.9 K gate with TSMC 0.25 um technology. It can encode 4.2 million pixels per second at 40 MHz.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages279-282
Number of pages4
DOIs
StatePublished - 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Country/TerritoryTaiwan
CityHsinchu
Period27/04/0529/04/05

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