Intra-channel reconfigurable interface for TSV and micro bump fault tolerance in 3-d RAMs

Kuan Te Wu, Jin Fu Li, Yun Chao Yu, Chih Sheng Hou, Chi Chun Yang, Ding Ming Kwai, Yung Fa Chou, Chih Yen Lo

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations


Three-dimensional (3-D) integration using through-silicon-via (TSV) is an emerging technology for integrated circuit (IC) design. It has been used in DRAM die stacking extensively. However, yield remains a key issue for volume production of 3-D RAMs. In this paper, we present a point-to-point interconnection structure derived from bus and propose a fault tolerance interface scheme for TSVs and micro bumps to enhance their manufacturing yield in the 3-D RAMs. The interconnection structure is inherently redundant and thus can replace defective TSVs or micro bumps without using repair circuits. Global and local reconfiguration approaches are proposed which benefit distinct situations of the 3-D RAM. Analyses show that the proposed intra-channel reconfigurable interconnection scheme can improve the yield of the 3-D RAM effectively. Compared to the previous solution using an inter-channel reconfigurable interconnection scheme, the yield improvement can be as large as 23% which is very significant.

Original languageEnglish
Title of host publicationProceedings - 23rd Asian Test Symposium, ATS 2014
PublisherIEEE Computer Society
Number of pages6
ISBN (Electronic)9781479960309
StatePublished - 7 Dec 2014
Event23rd Asian Test Symposium, ATS 2014 - Hangzhou, China
Duration: 16 Nov 201419 Nov 2014

Publication series

NameProceedings of the Asian Test Symposium
ISSN (Print)1081-7735


Conference23rd Asian Test Symposium, ATS 2014


  • 3-D IC
  • DRAM
  • fault tolerance
  • interface
  • TSV
  • yield enhancement


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