Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

B. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, M. Buehler, D. Caselli, S. Cekli, Vrsk Chaganti, Y. J. Chang, K. Chikkadi, T. Chu, T. CrimminsG. Darby, C. Ege, P. Elfick, T. Elko-Hansen, S. Fang, C. Gaddam, M. Ghoneim, H. Gomez, S. Govindaraju, Z. Guo, W. Hafez, M. Haran, M. Hattendorf, S. Hu, A. Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, S. Klopcic, D. Krishnan, J. Leib, Y. T. Lin, N. Lindert, G. Liu, O. Loh, Y. Luo, S. Mani, M. Mleczko, S. Mocherla, P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar, L. Pipes, P. Plekhanov, C. Prasad, M. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, J. R.Sanchez Perez, J. Sandford, A. Sathe, F. Shah, H. Shim, S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta, T. Troeger, X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, K. Yoon, N. Young

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).

Original languageEnglish
Title of host publication2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages282-283
Number of pages2
ISBN (Electronic)9781665497725
DOIs
StatePublished - 2022
Event2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States
Duration: 12 Jun 202217 Jun 2022

Publication series

NameDigest of Technical Papers - Symposium on VLSI Technology
Volume2022-June
ISSN (Print)0743-1562

Conference

Conference2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/TerritoryUnited States
CityHonolulu
Period12/06/2217/06/22

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