Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

B. Sell; S. An; J. Armstrong; D. Bahr; B. Bains; R. Bambery; K. Bang; D. Basu; S. Bendapudi; D. Bergstrom; R. Bhandavat; S. Bhowmick; M. Buehler; D. Caselli; S. Cekli; Vrsk Chaganti; Y. J. Chang; K. Chikkadi; T. Chu; T. Crimmins; G. Darby; C. Ege; P. Elfick; T. Elko-Hansen; S. Fang; C. Gaddam; M. Ghoneim; H. Gomez; S. Govindaraju; Z. Guo; W. Hafez; M. Haran; M. Hattendorf; S. Hu; A. Jain; S. Jaloviar; M. Jang; J. Kameswaran; V. Kapinus; A. Kennedy; S. Klopcic; D. Krishnan; J. Leib; Y. T. Lin; N. Lindert; G. Liu; O. Loh; Y. Luo; S. Mani; M. Mleczko; S. Mocherla; P. Packan; M. Paik; A. Paliwal; R. Pandey; K. Patankar; L. Pipes; P. Plekhanov; C. Prasad; M. Prince; G. Ramalingam; R. Ramaswamy; J. Riley; J. R.Sanchez Perez; J. Sandford; A. Sathe; F. Shah; H. Shim; S. Subramanian; S. Tandon; M. Tanniru; D. Thakurta; T. Troeger; X. Wang; C. Ward; A. Welsh; S. Wickramaratne; J. Wnuk; S. Q. Xu; P. Yashar; J. Yaung; K. Yoon; N. Young

doi:10.1109/VLSITechnologyandCir46769.2022.9830194

Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

B. Sell, S. An, J. Armstrong, D. Bahr, B. Bains, R. Bambery, K. Bang, D. Basu, S. Bendapudi, D. Bergstrom, R. Bhandavat, S. Bhowmick, M. Buehler, D. Caselli, S. Cekli, Vrsk Chaganti, Y. J. Chang, K. Chikkadi, T. Chu, T. CrimminsG. Darby, C. Ege, P. Elfick, T. Elko-Hansen, S. Fang, C. Gaddam, M. Ghoneim, H. Gomez, S. Govindaraju, Z. Guo, W. Hafez, M. Haran, M. Hattendorf, S. Hu, A. Jain, S. Jaloviar, M. Jang, J. Kameswaran, V. Kapinus, A. Kennedy, S. Klopcic, D. Krishnan, J. Leib, Y. T. Lin, N. Lindert, G. Liu, O. Loh, Y. Luo, S. Mani, M. Mleczko, S. Mocherla, P. Packan, M. Paik, A. Paliwal, R. Pandey, K. Patankar, L. Pipes, P. Plekhanov, C. Prasad, M. Prince, G. Ramalingam, R. Ramaswamy, J. Riley, J. R.Sanchez Perez, J. Sandford, A. Sathe, F. Shah, H. Shim, S. Subramanian, S. Tandon, M. Tanniru, D. Thakurta, T. Troeger, X. Wang, C. Ward, A. Welsh, S. Wickramaratne, J. Wnuk, S. Q. Xu, P. Yashar, J. Yaung, K. Yoon, N. Young

Department of Optics and Photonics

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

21 Scopus citations

Abstract

A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).

Original language	English
Title of host publication	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	282-283
Number of pages	2
ISBN (Electronic)	9781665497725
DOIs	https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830194
State	Published - 2022
Event	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States Duration: 12 Jun 2022 → 17 Jun 2022

Publication series

Name	Digest of Technical Papers - Symposium on VLSI Technology
Volume	2022-June
ISSN (Print)	0743-1562

Conference

Conference	2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022
Country/Territory	United States
City	Honolulu
Period	12/06/22 → 17/06/22

Access to Document

10.1109/VLSITechnologyandCir46769.2022.9830194

Cite this

Sell, B., An, S., Armstrong, J., Bahr, D., Bains, B., Bambery, R., Bang, K., Basu, D., Bendapudi, S., Bergstrom, D., Bhandavat, R., Bhowmick, S., Buehler, M., Caselli, D., Cekli, S., Chaganti, V., Chang, Y. J., Chikkadi, K., Chu, T., ... Young, N. (2022). Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 (pp. 282-283). (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830194

Sell, B. ; An, S. ; Armstrong, J. et al. / Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. pp. 282-283 (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing",

abstract = "A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).",

author = "B. Sell and S. An and J. Armstrong and D. Bahr and B. Bains and R. Bambery and K. Bang and D. Basu and S. Bendapudi and D. Bergstrom and R. Bhandavat and S. Bhowmick and M. Buehler and D. Caselli and S. Cekli and Vrsk Chaganti and Chang, {Y. J.} and K. Chikkadi and T. Chu and T. Crimmins and G. Darby and C. Ege and P. Elfick and T. Elko-Hansen and S. Fang and C. Gaddam and M. Ghoneim and H. Gomez and S. Govindaraju and Z. Guo and W. Hafez and M. Haran and M. Hattendorf and S. Hu and A. Jain and S. Jaloviar and M. Jang and J. Kameswaran and V. Kapinus and A. Kennedy and S. Klopcic and D. Krishnan and J. Leib and Lin, {Y. T.} and N. Lindert and G. Liu and O. Loh and Y. Luo and S. Mani and M. Mleczko and S. Mocherla and P. Packan and M. Paik and A. Paliwal and R. Pandey and K. Patankar and L. Pipes and P. Plekhanov and C. Prasad and M. Prince and G. Ramalingam and R. Ramaswamy and J. Riley and Perez, {J. R.Sanchez} and J. Sandford and A. Sathe and F. Shah and H. Shim and S. Subramanian and S. Tandon and M. Tanniru and D. Thakurta and T. Troeger and X. Wang and C. Ward and A. Welsh and S. Wickramaratne and J. Wnuk and Xu, {S. Q.} and P. Yashar and J. Yaung and K. Yoon and N. Young",

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Sell, B, An, S, Armstrong, J, Bahr, D, Bains, B, Bambery, R, Bang, K, Basu, D, Bendapudi, S, Bergstrom, D, Bhandavat, R, Bhowmick, S, Buehler, M, Caselli, D, Cekli, S, Chaganti, V, Chang, YJ, Chikkadi, K, Chu, T, Crimmins, T, Darby, G, Ege, C, Elfick, P, Elko-Hansen, T, Fang, S, Gaddam, C, Ghoneim, M, Gomez, H, Govindaraju, S, Guo, Z, Hafez, W, Haran, M, Hattendorf, M, Hu, S, Jain, A, Jaloviar, S, Jang, M, Kameswaran, J, Kapinus, V, Kennedy, A, Klopcic, S, Krishnan, D, Leib, J, Lin, YT, Lindert, N, Liu, G, Loh, O, Luo, Y, Mani, S, Mleczko, M, Mocherla, S, Packan, P, Paik, M, Paliwal, A, Pandey, R, Patankar, K, Pipes, L, Plekhanov, P, Prasad, C, Prince, M, Ramalingam, G, Ramaswamy, R, Riley, J, Perez, JRS, Sandford, J, Sathe, A, Shah, F, Shim, H, Subramanian, S, Tandon, S, Tanniru, M, Thakurta, D, Troeger, T, Wang, X, Ward, C, Welsh, A, Wickramaratne, S, Wnuk, J, Xu, SQ, Yashar, P, Yaung, J, Yoon, K & Young, N 2022, Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. in 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Digest of Technical Papers - Symposium on VLSI Technology, vol. 2022-June, Institute of Electrical and Electronics Engineers Inc., pp. 282-283, 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022, Honolulu, United States, 12/06/22. https://doi.org/10.1109/VLSITechnologyandCir46769.2022.9830194

Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. / Sell, B.; An, S.; Armstrong, J. et al.
2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc., 2022. p. 282-283 (Digest of Technical Papers - Symposium on VLSI Technology; Vol. 2022-June).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

AU - Sell, B.

AU - An, S.

AU - Armstrong, J.

AU - Bahr, D.

AU - Bains, B.

AU - Bambery, R.

AU - Bang, K.

AU - Basu, D.

AU - Bendapudi, S.

AU - Bergstrom, D.

AU - Bhandavat, R.

AU - Bhowmick, S.

AU - Buehler, M.

AU - Caselli, D.

AU - Cekli, S.

AU - Chaganti, Vrsk

AU - Chang, Y. J.

AU - Chikkadi, K.

AU - Chu, T.

AU - Crimmins, T.

AU - Darby, G.

AU - Ege, C.

AU - Elfick, P.

AU - Elko-Hansen, T.

AU - Fang, S.

AU - Gaddam, C.

AU - Ghoneim, M.

AU - Gomez, H.

AU - Govindaraju, S.

AU - Guo, Z.

AU - Hafez, W.

AU - Haran, M.

AU - Hattendorf, M.

AU - Hu, S.

AU - Jain, A.

AU - Jaloviar, S.

AU - Jang, M.

AU - Kameswaran, J.

AU - Kapinus, V.

AU - Kennedy, A.

AU - Klopcic, S.

AU - Krishnan, D.

AU - Leib, J.

AU - Lin, Y. T.

AU - Lindert, N.

AU - Liu, G.

AU - Loh, O.

AU - Luo, Y.

AU - Mani, S.

AU - Mleczko, M.

AU - Mocherla, S.

AU - Packan, P.

AU - Paik, M.

AU - Paliwal, A.

AU - Pandey, R.

AU - Patankar, K.

AU - Pipes, L.

AU - Plekhanov, P.

AU - Prasad, C.

AU - Prince, M.

AU - Ramalingam, G.

AU - Ramaswamy, R.

AU - Riley, J.

AU - Perez, J. R.Sanchez

AU - Sandford, J.

AU - Sathe, A.

AU - Shah, F.

AU - Shim, H.

AU - Subramanian, S.

AU - Tandon, S.

AU - Tanniru, M.

AU - Thakurta, D.

AU - Troeger, T.

AU - Wang, X.

AU - Ward, C.

AU - Welsh, A.

AU - Wickramaratne, S.

AU - Wnuk, J.

AU - Xu, S. Q.

AU - Yashar, P.

AU - Yaung, J.

AU - Yoon, K.

AU - Young, N.

PY - 2022

Y1 - 2022

N2 - A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).

AB - A new advanced CMOS FinFET technology, Intel 4, is introduced that extends Moore's law by offering 2X area scaling of the high performance logic library and greater than 20% performance gain at iso-power over Intel 7. The scaled high-performance library offers 50nm gate pitch, 30nm fin pitch and 30nm minimum metal pitch. This node delivers 8VT (4NVT + 4PVT) spanning a range of 190mV/180mV for N/PMOS, enabling designers to choose between power and speed requirements. EUV lithography is used extensively to simplify the process flow and improve yield. The interconnect stack features 16 metal layers with enhanced copper metallurgy at critical lower layers to deliver improved electromigration (EM) and lower line resistance (LR).

UR - http://www.scopus.com/inward/record.url?scp=85135238899&partnerID=8YFLogxK

U2 - 10.1109/VLSITechnologyandCir46769.2022.9830194

DO - 10.1109/VLSITechnologyandCir46769.2022.9830194

M3 - 會議論文篇章

AN - SCOPUS:85135238899

T3 - Digest of Technical Papers - Symposium on VLSI Technology

SP - 282

EP - 283

BT - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022

Y2 - 12 June 2022 through 17 June 2022

ER -

Sell B, An S, Armstrong J, Bahr D, Bains B, Bambery R et al. Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing. In 2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022. Institute of Electrical and Electronics Engineers Inc. 2022. p. 282-283. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSITechnologyandCir46769.2022.9830194

Intel 4 CMOS Technology Featuring Advanced FinFET Transistors optimized for High Density and High-Performance Computing

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