Innovative Practice on Wafer Test Innovations

Dyi Chung Hu, Hirohito Hashimoto, Li Fong Tseng, Ken Chau Cheung Cheng, Katherine Shu-Min Li, Sying Jyan Wang, Sean Y.S. Chen, Jwu E. Chen, Clark Liu, Andrew Huang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review


Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

Original languageEnglish
Title of host publicationProceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
PublisherIEEE Computer Society
ISBN (Electronic)9781728153599
StatePublished - Apr 2020
Event38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States
Duration: 5 Apr 20208 Apr 2020

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference38th IEEE VLSI Test Symposium, VTS 2020
Country/TerritoryUnited States
CitySan Diego


Dive into the research topics of 'Innovative Practice on Wafer Test Innovations'. Together they form a unique fingerprint.

Cite this