Innovative Practice on Wafer Test Innovations

Dyi Chung Hu; Hirohito Hashimoto; Li Fong Tseng; Ken Chau Cheung Cheng; Katherine Shu-Min Li; Sying Jyan Wang; Sean Y.S. Chen; Jwu E. Chen; Clark Liu; Andrew Huang

doi:10.1109/VTS48691.2020.9107619

Innovative Practice on Wafer Test Innovations

Dyi Chung Hu, Hirohito Hashimoto, Li Fong Tseng, Ken Chau Cheung Cheng, Katherine Shu-Min Li, Sying Jyan Wang, Sean Y.S. Chen, Jwu E. Chen, Clark Liu, Andrew Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

Original language	English
Title of host publication	Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020
Publisher	IEEE Computer Society
ISBN (Electronic)	9781728153599
DOIs	https://doi.org/10.1109/VTS48691.2020.9107619
State	Published - Apr 2020
Event	38th IEEE VLSI Test Symposium, VTS 2020 - San Diego, United States Duration: 5 Apr 2020 → 8 Apr 2020

Publication series

Name	Proceedings of the IEEE VLSI Test Symposium
Volume	2020-April

Conference

Conference	38th IEEE VLSI Test Symposium, VTS 2020
Country/Territory	United States
City	San Diego
Period	5/04/20 → 8/04/20

Access to Document

10.1109/VTS48691.2020.9107619

Cite this

Hu, D. C., Hashimoto, H., Tseng, L. F., Cheng, K. C. C., Shu-Min Li, K., Wang, S. J., Chen, S. Y. S., Chen, J. E., Liu, C., & Huang, A. (2020). Innovative Practice on Wafer Test Innovations. In Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020 Article 9107619 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2020-April). IEEE Computer Society. https://doi.org/10.1109/VTS48691.2020.9107619

@inproceedings{30b493b92e1743b89f501d8dcd76184b,

title = "Innovative Practice on Wafer Test Innovations",

abstract = "Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.",

author = "Hu, {Dyi Chung} and Hirohito Hashimoto and Tseng, {Li Fong} and Cheng, {Ken Chau Cheung} and {Shu-Min Li}, Katherine and Wang, {Sying Jyan} and Chen, {Sean Y.S.} and Chen, {Jwu E.} and Clark Liu and Andrew Huang",

note = "Publisher Copyright: {\textcopyright} 2020 IEEE.; 38th IEEE VLSI Test Symposium, VTS 2020 ; Conference date: 05-04-2020 Through 08-04-2020",

year = "2020",

month = apr,

doi = "10.1109/VTS48691.2020.9107619",

language = "???core.languages.en_GB???",

series = "Proceedings of the IEEE VLSI Test Symposium",

publisher = "IEEE Computer Society",

booktitle = "Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020",

}

Hu, DC, Hashimoto, H, Tseng, LF, Cheng, KCC, Shu-Min Li, K, Wang, SJ, Chen, SYS, Chen, JE, Liu, C & Huang, A 2020, Innovative Practice on Wafer Test Innovations. in Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020., 9107619, Proceedings of the IEEE VLSI Test Symposium, vol. 2020-April, IEEE Computer Society, 38th IEEE VLSI Test Symposium, VTS 2020, San Diego, United States, 5/04/20. https://doi.org/10.1109/VTS48691.2020.9107619

Innovative Practice on Wafer Test Innovations. / Hu, Dyi Chung; Hashimoto, Hirohito; Tseng, Li Fong et al.
Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020. IEEE Computer Society, 2020. 9107619 (Proceedings of the IEEE VLSI Test Symposium; Vol. 2020-April).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Innovative Practice on Wafer Test Innovations

AU - Hu, Dyi Chung

AU - Hashimoto, Hirohito

AU - Tseng, Li Fong

AU - Cheng, Ken Chau Cheung

AU - Shu-Min Li, Katherine

AU - Wang, Sying Jyan

AU - Chen, Sean Y.S.

AU - Chen, Jwu E.

AU - Liu, Clark

AU - Huang, Andrew

PY - 2020/4

Y1 - 2020/4

N2 - Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

AB - Wafer test integrates innovative works from upstream, automatic test equipment (ATE); middle stream, 2.3D/2.5D; and downstream, statistical analysis of randomness on wafer pattern recognition. NXP Taiwan proposes an AI-driven yield prediction of ATE to reduce test cost during frequent modification and changes in test systems. SiPlus proposes competitive 2.3D and SiPlus eHDF to compare many metrics with 2.5D interposer technology. Powertech Technology Inc. focuses the statistical analysis of randomness on conventional spatial wafer defect patterns. This session addresses an integrated innovation along test systems in ATE in upstream, then 2.3D/SiPlus eHDF integration structure design, finally novel randomness effects on wafer defect diagnosis.

UR - http://www.scopus.com/inward/record.url?scp=85086501220&partnerID=8YFLogxK

U2 - 10.1109/VTS48691.2020.9107619

DO - 10.1109/VTS48691.2020.9107619

M3 - 會議論文篇章

AN - SCOPUS:85086501220

T3 - Proceedings of the IEEE VLSI Test Symposium

BT - Proceedings - 2020 IEEE 38th VLSI Test Symposium, VTS 2020

PB - IEEE Computer Society

T2 - 38th IEEE VLSI Test Symposium, VTS 2020

Y2 - 5 April 2020 through 8 April 2020

ER -

Innovative Practice on Wafer Test Innovations

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