Inductance modeling for on-chip interconnects

Shang Wei Tu, Wen Zen Shen, Yao Wen Chang, Tai Chen Chen, Jing Yang Jou

Research output: Contribution to journalArticlepeer-review

5 Scopus citations


As the operation frequency reaches gigahertz in deep-submicron designs, the effects of inductance on noise and delay can no longer be neglected. Most of the previous works on inductance extraction are field-solvers, which are intrinsically more accurate but computationally expensive. Others focus on modeling the inductances of special routing topologies such as the bus structure. Therefore, it is not suitable to incorporate them on-line into a layout (placement and routing) tool for inductance (delay and noise) optimization. In this paper, we consider the overlapping of unequal wire lengths and dimensions to efficiently extract the loop inductance from the coplanar interconnect structure. The difference between our simulation results and the estimation values obtained by FastHenry [12] is within 10% for practical cases. In particular, our modeling is extremely efficient, and thus can be incorporated into a layout tool for inductance optimization.

Original languageEnglish
Pages (from-to)65-78
Number of pages14
JournalAnalog Integrated Circuits and Signal Processing
Issue number1
StatePublished - Apr 2003


  • Inductance
  • Interconnect
  • Layout
  • Modeling
  • Mutual inductance
  • Self inductance
  • Simulation


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