Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design

R. C. Hong; G. W. Chang; C. Y. Chao; Y. b. Chu; C. I. Chen

doi:10.1109/ICIEA.2010.5517124

Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design

R. C. Hong, G. W. Chang, C. Y. Chao, Y. b. Chu, C. I. Chen

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.

Original language	English
Title of host publication	Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010
Pages	492-497
Number of pages	6
DOIs	https://doi.org/10.1109/ICIEA.2010.5517124
State	Published - 2010
Event	5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010 - Taichung, Taiwan Duration: 15 Jun 2010 → 17 Jun 2010

Publication series

Name	Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010

Conference

Conference	5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010
Country/Territory	Taiwan
City	Taichung
Period	15/06/10 → 17/06/10

Keywords

Active power filter
Digital signal processor
Hardware-in-the-loop
Harmonics
Real-time simulation

Access to Document

10.1109/ICIEA.2010.5517124

Cite this

Hong, R. C., Chang, G. W., Chao, C. Y., Chu, Y. B., & Chen, C. I. (2010). Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design. In Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010 (pp. 492-497). Article 5517124 (Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010). https://doi.org/10.1109/ICIEA.2010.5517124

@inproceedings{35f0d64e9fbb44209e142c872ae38391,

title = "Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design",

abstract = "This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.",

keywords = "Active power filter, Digital signal processor, Hardware-in-the-loop, Harmonics, Real-time simulation",

author = "Hong, {R. C.} and Chang, {G. W.} and Chao, {C. Y.} and Chu, {Y. b.} and Chen, {C. I.}",

year = "2010",

doi = "10.1109/ICIEA.2010.5517124",

language = "???core.languages.en_GB???",

isbn = "9781424450466",

series = "Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010",

pages = "492--497",

booktitle = "Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010",

note = "5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010 ; Conference date: 15-06-2010 Through 17-06-2010",

}

Hong, RC, Chang, GW, Chao, CY, Chu, YB & Chen, CI 2010, Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design. in Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010., 5517124, Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010, pp. 492-497, 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010, Taichung, Taiwan, 15/06/10. https://doi.org/10.1109/ICIEA.2010.5517124

Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design. / Hong, R. C.; Chang, G. W.; Chao, C. Y. et al.
Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010. 2010. p. 492-497 5517124 (Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design

AU - Hong, R. C.

AU - Chang, G. W.

AU - Chao, C. Y.

AU - Chu, Y. b.

AU - Chen, C. I.

PY - 2010

Y1 - 2010

N2 - This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.

AB - This paper presents an approach of incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter (APF) design. Even when the three-phase source voltages are unbalanced and/or distorted and supply to a nonlinear load, the described compensation strategy can compensate the harmonic and neutral current, and thus improve the power factor. After verifying the efficiency of compensation strategy, the APF control strategy is embedded into the digital signal processor (DSP) to verify the feasibility of the proposed strategy on hardware in the loop (HIL) structure. Results show that the proposed approach is effective for shunt APF design.

KW - Active power filter

KW - Digital signal processor

KW - Hardware-in-the-loop

KW - Harmonics

KW - Real-time simulation

UR - http://www.scopus.com/inward/record.url?scp=77956038221&partnerID=8YFLogxK

U2 - 10.1109/ICIEA.2010.5517124

DO - 10.1109/ICIEA.2010.5517124

M3 - 會議論文篇章

AN - SCOPUS:77956038221

SN - 9781424450466

T3 - Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010

SP - 492

EP - 497

BT - Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010

T2 - 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010

Y2 - 15 June 2010 through 17 June 2010

ER -

Hong RC, Chang GW, Chao CY, Chu YB, Chen CI. Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design. In Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010. 2010. p. 492-497. 5517124. (Proceedings of the 2010 5th IEEE Conference on Industrial Electronics and Applications, ICIEA 2010). doi: 10.1109/ICIEA.2010.5517124

Incorporating hardware-in-the-loop simulation and ADALINE for shunt active power filter design

Abstract

Publication series

Conference

Keywords

Access to Document

Fingerprint

Cite this