Abstract
This work describes a new conditional-sum addition rule for low power applications. This conditional sum adder is especially attractive for implementing high-speed arithmetic systems. The new conditional sum addition rule can reduce the internal nodes and multiplexer numbers of the adder design. Various supply voltages and circuit structures are used to implement the new conditional sum adders. It's shown that about 10% to 25% power-delay product is saved.
| Original language | English |
|---|---|
| Pages (from-to) | 131-134 |
| Number of pages | 4 |
| Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
| State | Published - 1998 |
| Event | Proceedings of the 1998 11th Annual IEEE International ASIC Conference - Rochester, NY, USA Duration: 13 Sep 1998 → 16 Sep 1998 |