A fast and accurate power estimation of circuits is definitely required when the low power issues become more and more important. For large circuits, vector compaction techniques could provide a fast solution for power estimation with reasonable accuracy. In previous work , we proposed an efficient vector compaction method with grouping and single-sequence consecutive sampling technique for CMOS circuits. The single-sequence approach improved the losses on compaction ratio and speedup by minimizing the useless transitions in traditional random or random-liked sampling approaches but it still involved some undesired transitions. In this paper, we propose a new consecutive sampling technique, multi-sequence approach. It can dramatically reduce the useless transitions without involving any undesired transitions. Compared to the random sampling and the single-sequence approaches, the experimental results demonstrate that the average compaction ratio and the average speedup can be significantly improved with our multi-sequence approach.