Improved 32-bit conditional sum adder for low-power high-speed applications

Kuo Hsing Cheng, Shun Wen Cheng

Research output: Contribution to journalArticlepeer-review

7 Scopus citations

Abstract

This paper presents an improved 32-bit conditional sum adder. Due to architectural modification, the improved adder only selects and transmits carry signals; it therefore is named conditional carry adder (CCA). This 32-bit adder focuses on reducing the numbers of internal nodes and logical gates, while maintaining high speed. The 32-bit conditional sum adder uses 186 multiplexers, and the proposed 32-bit CCA only uses 129 multiplexers. Consequently, the proposed adder is attractive for use in low-power arithmetic systems. Conventional single-end static CMOS and differential-end CPL circuits were used to implement and compare the proposed 32-bit CCA. Experimental and control chips were designed and fabricated using 0.5μm CMOS technology. Simulations and measurements under various supply voltages showed that the 32-bit CCA achieved high performance in low-voltage high-speed applications.

Original languageEnglish
Pages (from-to)975-989
Number of pages15
JournalJournal of Information Science and Engineering
Volume22
Issue number4
StatePublished - Jul 2006

Keywords

  • 32-bit
  • Carry select adder
  • CMOS design
  • Conditional sum adder
  • Differential-end logic
  • High-speed
  • Low-voltage
  • Pass-transistor logic

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