Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung Han Tsai; Yuan Chen Ho; Ming Hwa Sheu

doi:10.1109/DDECS.2019.8724665

Implementation of FPGA-based Accelerator for Deep Neural Networks

Tsung Han Tsai, Yuan Chen Ho, Ming Hwa Sheu

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

22 Scopus citations

Abstract

At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network (CNN) has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages of low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.

Original language	English
Title of host publication	Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781728100739
DOIs	https://doi.org/10.1109/DDECS.2019.8724665
State	Published - Apr 2019
Event	22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 - Cluj-Napoca, Romania Duration: 24 Apr 2019 → 26 Apr 2019

Publication series

Name	Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

Conference

Conference	22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019
Country/Territory	Romania
City	Cluj-Napoca
Period	24/04/19 → 26/04/19

Keywords

CNN
DNN
FPGA
hardware accelerator
low utilization

Access to Document

10.1109/DDECS.2019.8724665

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Tsai, T. H., Ho, Y. C., & Sheu, M. H. (2019). Implementation of FPGA-based Accelerator for Deep Neural Networks. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 Article 8724665 (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/DDECS.2019.8724665

Tsai, Tsung Han ; Ho, Yuan Chen ; Sheu, Ming Hwa. / Implementation of FPGA-based Accelerator for Deep Neural Networks. Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).

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title = "Implementation of FPGA-based Accelerator for Deep Neural Networks",

abstract = "At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network (CNN) has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages of low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.",

keywords = "CNN, DNN, FPGA, hardware accelerator, low utilization",

author = "Tsai, {Tsung Han} and Ho, {Yuan Chen} and Sheu, {Ming Hwa}",

note = "Publisher Copyright: {\textcopyright} 2019 IEEE.; 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019 ; Conference date: 24-04-2019 Through 26-04-2019",

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series = "Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",

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Tsai, TH, Ho, YC & Sheu, MH 2019, Implementation of FPGA-based Accelerator for Deep Neural Networks. in Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019., 8724665, Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019, Institute of Electrical and Electronics Engineers Inc., 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019, Cluj-Napoca, Romania, 24/04/19. https://doi.org/10.1109/DDECS.2019.8724665

Implementation of FPGA-based Accelerator for Deep Neural Networks. / Tsai, Tsung Han; Ho, Yuan Chen; Sheu, Ming Hwa.
Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. 8724665 (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - At present, there are many researches on deep neural network (DNN) applied in life. In the task of object recognition, deep convolutional neural network (CNN) has a good performance, but it relies on GPU to solve a large number of complex operations. Thus the hardware accelerator of DNN is concerned by many people. In order to implement the DNN model on hardware, complex connection relationship and memory usage scheduling are needed. This paper presnets the design of FPGA-based accelerator for DNN. The proposed architecture is implemented on Xilinx Zynq-7020 FPGA. It takes the advantages of low latency and low usage in the task of MNIST digital identification, and keeps the 96 % recognition rate.

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Tsai TH, Ho YC, Sheu MH. Implementation of FPGA-based Accelerator for Deep Neural Networks. In Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. 8724665. (Proceedings - 2019 22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019). doi: 10.1109/DDECS.2019.8724665

Implementation of FPGA-based Accelerator for Deep Neural Networks

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