Implementation of a delta-sigma analog-to-digital converter

Chin Fa Hsieh, Tsung Han Tsai, Chun Sheng Chen, Yu Hao Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

The sigma-delta analog-to-digital converter (ADC) has less consumption of circuit power and can achieve higher resolution. In this chapter, a sigma-delta ADC which contains a second-order sigma-delta modulator is presented. The modulator architecture is first designed by using the behavioral simulation of MATLAB, and then the TSMC 0.18 μm single-poly six-metal process. Layout of each analog block has been shown. Simulation results show that, with an input of a 6 dB 1 kHz sine, the delta-sigma ADC can achieve an SNR of 87.2 dB. The core size is 0.6456 mm 0.3340 mm. With a 16-bit resolution, it is suitable for audio applications.

Original languageEnglish
Title of host publicationProceedings of the 3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
EditorsJengnan Juang
PublisherSpringer Verlag
Pages257-262
Number of pages6
ISBN (Print)9783319173139
DOIs
StatePublished - 2016
Event3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014 - Kaohsiung, Taiwan
Duration: 19 Dec 201421 Dec 2014

Publication series

NameLecture Notes in Electrical Engineering
Volume345
ISSN (Print)1876-1100
ISSN (Electronic)1876-1119

Conference

Conference3rd International Conference on Intelligent Technologies and Engineering Systems, ICITES 2014
Country/TerritoryTaiwan
CityKaohsiung
Period19/12/1421/12/14

Keywords

  • ADC
  • Modulation
  • Sigma-delta

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