Impact of capacitance correlation on yield enhancement of mixed-signal/analog integrated circuits

Pei Wen Luo, Jwu E. Chen, Chin Long Wey, Liang Chia Cheng, Ji Jan Chen, Wen Ching Wu

Research output: Contribution to journalArticlepeer-review

32 Scopus citations

Abstract

Random fluctuations in process conditions change the physical properties of parameters on a chip. The correlation of device parameters depends on spatial locations. In general, the closer devices most likely have the similar parameter variation. The key performance of many analog circuits is directly related to accurate capacitance ratios. Parallel unit capacitances have a great effect on reducing ratio mismatch. This paper addresses the impact of capacitance correlation on the yield enhancement of mixed-signal/analog integrated circuits. The relationship between correlation and variation of capacitance ratio is also presented. Therefore, both mismatch and variation of capacitance ratio can be expressed in terms of capacitance correlation. Furthermore, both process variation and device mismatch are considered in the early design phase to reduce the design costs and speed up the time to market.

Original languageEnglish
Article number4655559
Pages (from-to)2097-2101
Number of pages5
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume27
Issue number11
DOIs
StatePublished - Nov 2008

Keywords

  • Capacitance ratio
  • Common centroid
  • Mismatch
  • Process variation
  • Spatial correlation
  • Yield analysis

Fingerprint

Dive into the research topics of 'Impact of capacitance correlation on yield enhancement of mixed-signal/analog integrated circuits'. Together they form a unique fingerprint.

Cite this