High voltage power MOSFET with reduced JFET area design

Feng Tso Chien, Tien Chun Li, Ping Hung Lai, Chien Nan Liao, Yao Tsung Tsai

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A high voltage power vertical double-diffused MOSFET with reduced JFET area by using an overall implantation was discussed. The reduced JFET area realizes a low gate charge and a high switching speed, due to the reduction of the gate-drain overlapped area. The measured gate-drain charge and gate charge can be improved by 61.1% and 71.8 %, respectively. The F.O.M of the proposed device and the conventional one is 64.4 nΩ×C and 190.9 nΩ×C, respectively. We also discussed the reliability issue and compared the avalanche capability to the proposed structure and the conventional device. The ruggedness of the proposed devices can be improved by a higher cell density design with a planar oxide self align p+ implantation process.

Original languageEnglish
Title of host publication2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010
Pages526-529
Number of pages4
DOIs
StatePublished - 2010
Event2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010 - Hefei, China
Duration: 16 Jun 201018 Jun 2010

Publication series

Name2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010

Conference

Conference2nd International Symposium on Power Electronics for Distributed Generation Systems, PEDG 2010
Country/TerritoryChina
CityHefei
Period16/06/1018/06/10

Keywords

  • Figure of merit (F.O.M.)
  • Gate charge
  • Power VDMOSFET
  • Unclamped inductive load switching (UIS)

Fingerprint

Dive into the research topics of 'High voltage power MOSFET with reduced JFET area design'. Together they form a unique fingerprint.

Cite this