@inproceedings{9d12690dd49b460f9ea419c755c38941,
title = "High-speed four-phase CMOS logic for complex high-speed VLSI",
abstract = "In this paper, a new four-phase dynamic logic, called the high-speed precharge-discharge CMOS logic (HS-PDCMOS logic) is proposed and analyzed. Basically the HS-PDCMOS logic uses two different units to implement the logic function and to drive the output load separately. Thus a complex function can be implemented within a single gate and achieve a high operation speed. The HS-PDCMOS logic needs four operation clocks and has three different versions. An experimental chip has been designed and measured to verify partly the results of circuit analysis and simulation. It is shown that the HS-PDCMOS has an operation speed about 2.5 to 3 times higher than the conventional four-phase dynamic logic. Moreover, the new logic has no problems of clock skew, race, and charge redistribution.",
author = "Wu, {Chung Yu} and Cheng, {Kuo Hsing} and Wang, {Jinn Shyan}",
note = "Publisher Copyright: {\textcopyright} 1992 IEEE.; 1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992 ; Conference date: 10-05-1992 Through 13-05-1992",
year = "1992",
doi = "10.1109/ISCAS.1992.230269",
language = "???core.languages.en_GB???",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "1288--1291",
booktitle = "1992 IEEE International Symposium on Circuits and Systems, ISCAS 1992",
}