High-speed and ultra-low-voltage divide-by-4/5 counter for frequency synthesizer

Yu Lung Lo, Wei Bin Yang, Ting Sheng Chao, Kuo Hsing Cheng

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


A high-speed and ultra-low-voltage divide-by-4/5 counter with dynamic floating input D flip-flop (DFIDFF) is presented in this paper. The proposed DFIDFF and control logic gates are merged to reduce effective capacitance of internal and external nodes, and increase the operating speed of divide-by-4/5 counter. The proposed divide-by-4/5 counter is fabricated in a 0.13-μm CMOS process. The measured maximum operating frequency and power consumption of the counter are 600 MHz and 8.35 μW at a 0.5 V supply voltage. HSPICE simulations demonstrate that the proposed counter (divide-by-4) reduces power-delay product (PDP) by 37%, 71%, and 57% from those of the TGFF counter, Yang's counter [1], and the E-TSPC counter [2], respectively.

Original languageEnglish
Pages (from-to)890-893
Number of pages4
JournalIEICE Transactions on Electronics
Issue number6
StatePublished - 2009


  • Counters
  • Dynamic D flip-flops
  • Prescalers
  • Ultra-low-voltage design


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