High-performance double-channel poly-silicon thin-film transistor with raised drain and reduced drain electric field structures

Feng Tso Chien, Chien Nan Liao, Chin Mu Fang, Yao Tsung Tsai

Research output: Contribution to journalArticlepeer-review

5 Scopus citations

Abstract

In this paper, a high-performance single-gate double-channel polycrystalline-silicon thin-film transistor (DCTFT) is proposed and experimentally demonstrated for the first time. Two thin channels, accompanied with a raised source/drain (S/D) area, an offset structure, a drain field plate, and a field-induced drain region, are used in this device, allowing a lower S/D resistance and a better device performance. Our experimental results show that the on-current of the DCTFT is higher than that of the conventional structure, and the leakage current is greatly reduced simultaneously. In addition, the device stability, such as threshold voltage shift and drain on-current degradation under a high gate bias, is also improved by the design of two channels and the reduced drain electric field structures. The lower drain electric field of the DCTFT is also beneficial to scaling down the device for a better performance.

Original languageEnglish
Pages (from-to)441-447
Number of pages7
JournalIEEE Transactions on Electron Devices
Volume56
Issue number3
DOIs
StatePublished - 2009

Keywords

  • Double-channel poly-Si thin-film transistor (DCTFT)
  • Raised source/drain (RSD)

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