@inproceedings{f1ac7a3aacd74c88bc683b1a12fa8708,
title = "High-performance 3D-SRAM architecture design",
abstract = "A high-performance three-dimension (3D) static random access memory (SRAM) architecture design is presented in this paper. The emerging 3D integration technology involves stacking two or more die connected with a very high density and low latency interface. By using array splitting and bank stacking approaches, the wire length of the proposed 3D SRAM architecture design can be effectively reduced resulting in latency and energy reduction benefits. Performance evaluation results show that about 35.8% latency reduction and 29.4% energy saving can be achieved for a 16MB 4-layer stacked 3D SRAM array. With different sizes of a SRAM array, the proposed 3D architecture has also demonstrated great improvement in latency and energy over the conventional 2D design.",
keywords = "3D SRAM, energy consumption, High-performance, latency",
author = "Hsu, {Chun Lung} and Wu, {Ching Fen}",
year = "2010",
doi = "10.1109/APCCAS.2010.5774741",
language = "???core.languages.en_GB???",
isbn = "9781424474561",
series = "IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS",
pages = "907--910",
booktitle = "Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010",
note = "2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 ; Conference date: 06-12-2010 Through 09-12-2010",
}