High-performance 3D-SRAM architecture design

Chun Lung Hsu, Ching Fen Wu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

A high-performance three-dimension (3D) static random access memory (SRAM) architecture design is presented in this paper. The emerging 3D integration technology involves stacking two or more die connected with a very high density and low latency interface. By using array splitting and bank stacking approaches, the wire length of the proposed 3D SRAM architecture design can be effectively reduced resulting in latency and energy reduction benefits. Performance evaluation results show that about 35.8% latency reduction and 29.4% energy saving can be achieved for a 16MB 4-layer stacked 3D SRAM array. With different sizes of a SRAM array, the proposed 3D architecture has also demonstrated great improvement in latency and energy over the conventional 2D design.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages907-910
Number of pages4
DOIs
StatePublished - 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: 6 Dec 20109 Dec 2010

Publication series

NameIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS

Conference

Conference2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/TerritoryMalaysia
CityKuala Lumpur
Period6/12/109/12/10

Keywords

  • 3D SRAM
  • energy consumption
  • High-performance
  • latency

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