In this work, we use a high-level design methodology for the rapid hardware synthesis of a complex smart sensor network (SSN) system. The GRAFCET is then used to model the individual functional modules and the hierarchical behavior of the system. The behavior of each module is represented as a sequential–concurrent hybrid discrete event system. We apply high-level synthesis rules to generate a VHSIC hardware description language (VHDL)-target efficient hardware for a smart sensor controller and smart gateway controller. Finally, these embedded hardware controllers are generated automatically to integrate all intelligent functional modules into a complex embedded system, and a hardware circuit is then synthesized. The experimental results show that the hardware circuit can meet the definition of an SSN system for Industrial Internet of Things applications. Moreover, this methodology enables a coherent design quality, short design period, low development cost, and short time-to-market for complex industrial applications.
- Discrete-event modeling
- High-level synthesis
- Industrial Internet of Things (IIoT)
- Smart sensor network