High efficient H.264/AVC deblocking filter architecture for real-time QFHD

Tsung Han Tsai, Yu Nan Pan

Research output: Contribution to journalArticlepeer-review

13 Scopus citations

Abstract

This paper proposes a novel processing order and an efficient architecture for real-time implementation of the deblocking filter in H.264/AVC video coding standard. The process of the deblocking filter causes the intensive requirement of data and computations and increases the execution time of both encoding and decoding. The proposed processing order, double-cross processing order, is effectively constructed by a parallel flow to improve processing speed and reduce memory access. Moreover, the proposed architecture can save about 38- 80% of memory access as compared with other designs. Based on this high efficient architecture, the processing performance can be enhanced, and the operation frequency for standardized video specifications can be reduced. For the general video specification HDTV1080p (1920 × 1080 @30fps), the operation frequency of the proposed architecture is only 11.5 MHz. For the high resolution QFHD specification (3840 × 2160 @30fps), the operation frequency of the proposed architecture is only 46.6 MHz. The implementation result is about 20.14K gates, and the memory requirement is 64 × 32 bits. The power dissipation for QFHD specification is 7.7 mW at 46.6 MHz operating frequency.1

Original languageEnglish
Article number5373795
Pages (from-to)2248-2256
Number of pages9
JournalIEEE Transactions on Consumer Electronics
Volume55
Issue number4
DOIs
StatePublished - Nov 2009

Keywords

  • Deblocking filter
  • H.264/AVC
  • Memory efficient
  • QFHD

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