High efficient 3-input XOR for low-voltage low-power high-speed applications

Kuo Hsing Cheng, Ven Chieh Hsieh

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

5 Scopus citations

Abstract

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages166-169
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
StatePublished - 1999
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 23 Aug 199925 Aug 1999

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/TerritoryKorea, Republic of
CitySeoul
Period23/08/9925/08/99

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