High efficient 3-input XOR for low-voltage low-power high-speed applications

Kuo Hsing Cheng; Ven Chieh Hsieh

doi:10.1109/APASIC.1999.824054

High efficient 3-input XOR for low-voltage low-power high-speed applications

Kuo Hsing Cheng, Ven Chieh Hsieh

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

Original language	English
Title of host publication	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	166-169
Number of pages	4
ISBN (Print)	0780357051, 9780780357051
DOIs	https://doi.org/10.1109/APASIC.1999.824054
State	Published - 1999
Event	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of Duration: 23 Aug 1999 → 25 Aug 1999

Publication series

Name	AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Conference

Conference	1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
Country/Territory	Korea, Republic of
City	Seoul
Period	23/08/99 → 25/08/99

Access to Document

10.1109/APASIC.1999.824054

Cite this

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title = "High efficient 3-input XOR for low-voltage low-power high-speed applications",

abstract = "A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.",

author = "Cheng, {Kuo Hsing} and Hsieh, {Ven Chieh}",

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Cheng, KH & Hsieh, VC 1999, High efficient 3-input XOR for low-voltage low-power high-speed applications. in AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs., 824054, AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs, Institute of Electrical and Electronics Engineers Inc., pp. 166-169, 1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999, Seoul, Korea, Republic of, 23/08/99. https://doi.org/10.1109/APASIC.1999.824054

High efficient 3-input XOR for low-voltage low-power high-speed applications. / Cheng, Kuo Hsing; Hsieh, Ven Chieh.
AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs. Institute of Electrical and Electronics Engineers Inc., 1999. p. 166-169 824054 (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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N2 - A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

AB - A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

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Y2 - 23 August 1999 through 25 August 1999

ER -

High efficient 3-input XOR for low-voltage low-power high-speed applications

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