High efficiency architecture of fast block motion estimation with real-time QFHD on H.264 video coding

Tsai Tsung-Han, Pan Yu-Nan

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations

Abstract

The H.264/AVC inter-prediction is performed for Variable Block-Size Motion Estimation (VBSME) such as 16×16, 16×8, 8×16, 8×8, 8×4, 4×8 and 4×4, it cause the high complexity for H.264 Motion Estimation (ME). This investigation develops an architecture for a combined fast motion estimation algorithm with Edge Information Mode Decision (EIMD) and Predict Hexagon Search (PHS). Compared with other popular ME architecture, the proposed architecture has a large search range and low processing frequency. For the general specification of SDTV (720×480) with 4 reference frames, search range 256×256, the proposed architecture needs only 18.66MHz. For the very high specification of QFHD (3840×2160) with 1 reference frame, search range 256×256, the proposed architecture only requires 112MHz. The gate count of the proposed architecture is 300K, and the memory usage is 12.6 KB.

Original languageEnglish
Title of host publicationProceedings - 10th IEEE International Symposium on Multimedia, ISM 2008
Pages124-129
Number of pages6
DOIs
StatePublished - 2008
Event10th IEEE International Symposium on Multimedia, ISM 2008 - Berkeley, CA, United States
Duration: 15 Dec 200817 Dec 2008

Publication series

NameProceedings - 10th IEEE International Symposium on Multimedia, ISM 2008

Conference

Conference10th IEEE International Symposium on Multimedia, ISM 2008
Country/TerritoryUnited States
CityBerkeley, CA
Period15/12/0817/12/08

Keywords

  • Fast block matching algorithm
  • H.264
  • High efficiency architecture
  • Motion estimation
  • QFHD

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