For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm2.