High accuracy jitter measurement using cyclic pulse width modulation structure

Kuo Hsing Cheng, Shu Yu Jiang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

For high-speed circuit testing, traditional ways are not enough in measuring the clock jitter. The probe's loading effect would distort the tested clock signal and change the measurement result. Even some BIST techniques can release this problem. There is still a conflict between the circuit area and the timing resolution in the existing BIST techniques. The cyclic pulse width modulation structure is used to release this problem. The hardware overhead problem is released and the demanded resolution also can be reached. Furthermore, the effect of the PVTL is also released. The simulation result is based on TSMC 0.25um CMOS process. The selectable resolution is from 9ps to 20ps and the area is 0.039mm2.

Original languageEnglish
Title of host publication2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Pages24-27
Number of pages4
DOIs
StatePublished - 2005
Event2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT) - Hsinchu, Taiwan
Duration: 27 Apr 200529 Apr 2005

Publication series

Name2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Volume2005

Conference

Conference2005 IEEE VLSI-TSA International Symposium on VLSI Design, Automation and Test,(VLSI-TSA-DAT)
Country/TerritoryTaiwan
CityHsinchu
Period27/04/0529/04/05

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