Hierarchical test integration methodology for 3-D ICs

Che Wei Chou, Jin Fu Li, Yun Chao Yu, Chih Yen Lo, Ding Ming Kwai, Yung Fa Chou

Research output: Contribution to journal › Comment/debate

5 Scopus citations

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title = "Hierarchical test integration methodology for 3-D ICs",

author = "Chou, {Che Wei} and Li, {Jin Fu} and Yu, {Yun Chao} and Lo, {Chih Yen} and Kwai, {Ding Ming} and Chou, {Yung Fa}",

year = "2015",

month = jul,

day = "1",

doi = "10.1109/MDAT.2015.2427257",

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volume = "32",

pages = "59--70",

journal = "IEEE Design and Test",

issn = "2168-2356",

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TY - JOUR

T1 - Hierarchical test integration methodology for 3-D ICs

AU - Chou, Che Wei

AU - Li, Jin Fu

AU - Yu, Yun Chao

AU - Lo, Chih Yen

AU - Kwai, Ding Ming

AU - Chou, Yung Fa

PY - 2015/7/1

Y1 - 2015/7/1

UR - http://www.scopus.com/inward/record.url?scp=84936750057&partnerID=8YFLogxK

U2 - 10.1109/MDAT.2015.2427257

DO - 10.1109/MDAT.2015.2427257

M3 - 評論/辯論

AN - SCOPUS:84936750057

SN - 2168-2356

VL - 32

SP - 59

EP - 70

JO - IEEE Design and Test

JF - IEEE Design and Test

IS - 4

M1 - 7096969

ER -