Hierarchical floorplan design on the internet

Jiann Horng Lin; Jing Yang Jou; Hui Ru Jiang

doi:10.1109/ASPDAC.1999.759992

Hierarchical floorplan design on the internet

Jiann Horng Lin
, Jing Yang Jou
, Hui Ru Jiang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

With the proliferation of transistor count in VLSI design, more and more design groups try to figure out a way to efficiently combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical floorplan design can be adequately solved in the Internet environment. In this paper, we address the problem of area minimization floorplan design in the Internet environment. We propose a novel algorithm, RMG algorithm. Taking advantage of the Internet, RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. With creating floorplan design in the Internet environment, it can be seen that the Internet advantages Electronic Design Automation (EDA).

Original language	English
Title of host publication	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	189-192
Number of pages	4
ISBN (Electronic)	078035012X
DOIs	https://doi.org/10.1109/ASPDAC.1999.759992
State	Published - 1999
Event	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 - Wanchai, Hong Kong Duration: 18 Jan 1999 → 21 Jan 1999

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1999-January

Conference

Conference	4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Country/Territory	Hong Kong
City	Wanchai
Period	18/01/99 → 21/01/99

Access to Document

10.1109/ASPDAC.1999.759992

Cite this

Lin, J. H., Jou, J. Y., & Jiang, H. R. (1999). Hierarchical floorplan design on the internet. In Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999 (pp. 189-192). Article 759992 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1999-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASPDAC.1999.759992

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title = "Hierarchical floorplan design on the internet",

abstract = "With the proliferation of transistor count in VLSI design, more and more design groups try to figure out a way to efficiently combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical floorplan design can be adequately solved in the Internet environment. In this paper, we address the problem of area minimization floorplan design in the Internet environment. We propose a novel algorithm, RMG algorithm. Taking advantage of the Internet, RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. With creating floorplan design in the Internet environment, it can be seen that the Internet advantages Electronic Design Automation (EDA).",

author = "Lin, \{Jiann Horng\} and Jou, \{Jing Yang\} and Jiang, \{Hui Ru\}",

note = "Publisher Copyright: {\textcopyright} 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.; 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999 ; Conference date: 18-01-1999 Through 21-01-1999",

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series = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

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Lin, JH, Jou, JY & Jiang, HR 1999, Hierarchical floorplan design on the internet. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999., 759992, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1999-January, Institute of Electrical and Electronics Engineers Inc., pp. 189-192, 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999, Wanchai, Hong Kong, 18/01/99. https://doi.org/10.1109/ASPDAC.1999.759992

Hierarchical floorplan design on the internet. / Lin, Jiann Horng; Jou, Jing Yang; Jiang, Hui Ru.
Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999. Institute of Electrical and Electronics Engineers Inc., 1999. p. 189-192 759992 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1999-January).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - With the proliferation of transistor count in VLSI design, more and more design groups try to figure out a way to efficiently combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical floorplan design can be adequately solved in the Internet environment. In this paper, we address the problem of area minimization floorplan design in the Internet environment. We propose a novel algorithm, RMG algorithm. Taking advantage of the Internet, RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. With creating floorplan design in the Internet environment, it can be seen that the Internet advantages Electronic Design Automation (EDA).

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DO - 10.1109/ASPDAC.1999.759992

M3 - 會議論文篇章

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BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999

Y2 - 18 January 1999 through 21 January 1999

ER -

Hierarchical floorplan design on the internet

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