@inproceedings{865861b25cc04a0b894e41da63030657,
title = "Hierarchical architecture for network-on-chip platform",
abstract = "In this paper. we propose one hierarchical 2-D mesh Network-on-chip (NoC) platform to support applications with the complexity of several hundreds of tasks or with huge amount of transmission data. Moreover, applying the task binding method by considering communication amount. communication data contention and bandwidlh penalty to enhance the system overall performance of the new architecture. Modeling the NoC system data transmission behavior at system level is applied to predict system overall performance and an automatic NoC system performance simulation tool is also built. Therefore, architecture and designers can predict the system performance and obtain all parameters of the designed platform at system abstraction level. The experimental results show that the overall system throughput. the latency, and the saving of redundant transactions are improved by 27%, 14.4% and 21.8% respectively under the communication dominated situation.",
author = "Lin, {Liang Yu} and Lin, {Huang Kai} and Wang, {Cheng Yeh} and Van, {Lan Da} and Jou, {Jing Yang}",
year = "2009",
doi = "10.1109/VDAT.2009.5158165",
language = "???core.languages.en_GB???",
isbn = "9781424427826",
series = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",
pages = "343--346",
booktitle = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09",
note = "2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09 ; Conference date: 28-04-2009 Through 30-04-2009",
}