Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement

Katherine Shu Min Li, Peter Yi Yu Liao, Ken Chau Cheung Cheng, Leon Li Yang Chen, Sying Jyan Wang, Andrew Yi Ann Huang, Leon Chou, Gus Chang Hung Han, Jwu E. Chen, Hsin Chung Liang, Chung Lung Hsu

Research output: Contribution to journalArticlepeer-review

Abstract

Wafer map defect pattern recognition provides useful clues to yield learning. However, most wafer maps have no special spatial patterns and are full of noises, which make pattern recognition difficult. Especially, recognizing scratch and line types of defect patterns is challenging for process and test engineers. It takes a lot of manpower to identify such patterns, as hidden defective dies may exist on the scratch contour and become discontinuity points. Hidden scratch defective dies may suffer from latent and leakage faults, which usually deteriorate quickly and need to be screened by burn-in test to improve quality. A possible solution is to locate the obscure defective dies in scratch patterns and mark them as faulty. As a result, the quality and reliability of products is significantly improved and cost of final test is reduced. In this article, we propose a systematic methodology to search for potential hidden scratch/line defects in wafers. A five-phase method is developed to enhance wafer maps such that automatic hidden scratch defect pattern recognition can be carried out with high accuracy. Experimental results show the proposed method achieves higher than 89% recognition rate for scratch/line patterns, and higher than 94% for all common wafer defect pattern types.

Original languageEnglish
Article number9273073
Pages (from-to)9-16
Number of pages8
JournalIEEE Transactions on Semiconductor Manufacturing
Volume34
Issue number1
DOIs
StatePublished - Feb 2021

Keywords

  • Wafer map
  • clustering
  • defect pattern
  • line
  • machine learning
  • scratch
  • yield learning

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