TY - JOUR
T1 - Hardware implementation of EMD using DSP and FPGA for online signal processing
AU - Lee, Ming Huan
AU - Shyu, Kuo Kai
AU - Lee, Po Lei
AU - Huang, Chien Ming
AU - Chiu, Yun Jen
N1 - Funding Information:
Manuscript received August 29, 2009; revised December 15, 2009 and March 15, 2010; accepted June 2, 2010. Date of publication July 23, 2010; date of current version May 13, 2011. This work was supported by the National Science Council of Taiwan under Grant NSC 96-2221-E-008089-MY3.
PY - 2011/6
Y1 - 2011/6
N2 - This paper combines a digital signal processor (DSP) and a field programmable gate array (FPGA) to realize the online empirical mode decomposition (EMD)-based signal processing system. The EMD algorithm is a novel signal analysis technique, decomposing signals into a series of intrinsic mode functions. First, the EMD algorithm is implemented in the DSP, named the EMD processor, which has the ability to eliminate noise from the original signal. Next, in order to process the online sequential signal, this paper proposes and implements pipeline and data transfer controllers in the FPGA, called the data processing flow processor. Then, the data processing flow processor coordinates the EMD processor, analog-to-digital converter, and digital-to-analog converter module boards. Finally, this paper presents a prototype of the online EMD-based electrocardiogram denoise system to verify the features of the proposed architecture. The emulations and experimental results demonstrate the effectiveness of the presented system as expected.
AB - This paper combines a digital signal processor (DSP) and a field programmable gate array (FPGA) to realize the online empirical mode decomposition (EMD)-based signal processing system. The EMD algorithm is a novel signal analysis technique, decomposing signals into a series of intrinsic mode functions. First, the EMD algorithm is implemented in the DSP, named the EMD processor, which has the ability to eliminate noise from the original signal. Next, in order to process the online sequential signal, this paper proposes and implements pipeline and data transfer controllers in the FPGA, called the data processing flow processor. Then, the data processing flow processor coordinates the EMD processor, analog-to-digital converter, and digital-to-analog converter module boards. Finally, this paper presents a prototype of the online EMD-based electrocardiogram denoise system to verify the features of the proposed architecture. The emulations and experimental results demonstrate the effectiveness of the presented system as expected.
KW - Digital signal processor (DSP)
KW - empirical mode decomposition (EMD)
KW - field programmable gate array (FPGA)
UR - http://www.scopus.com/inward/record.url?scp=79956283096&partnerID=8YFLogxK
U2 - 10.1109/TIE.2010.2060454
DO - 10.1109/TIE.2010.2060454
M3 - 期刊論文
AN - SCOPUS:79956283096
SN - 0278-0046
VL - 58
SP - 2473
EP - 2481
JO - IEEE Transactions on Industrial Electronics
JF - IEEE Transactions on Industrial Electronics
IS - 6
M1 - 5518428
ER -