@inproceedings{5d907ee0b10d4064a5ef2abd0fe7d50c,
title = "Hardware design of the scalable video encoder for the multi-source digital home environment",
abstract = "In this paper, hardware realization of the scalable video compressor encoder is proposed to achieve the requirement of the multi-source digital home environment. The Proposed 2-D DWT architecture is composed of two 1-D DWT and internal buffer. Moreover, the parallel scanning method is realized to reduce the internal buffer size instead of the conventional line-based scanning method. On the other hand, a pipelined MQ encoder architecture is also proposed to increase the throughput. After the synthesis, the throughput of proposed hardware realization is 93.3M samples/sec by adopting 0.18 μm CMOS technology. The power dissipation is 48.22 mW under 100 MHz clock source. The throughput meets the requirement of real-time processing of a 720p/30 fps video sequence, demanded by the digital home environment.",
keywords = "image compression, Lossless compression, quality driven bit plane sequencer, size scalability, SNR scalability, video compression",
author = "Li, {Zong Hong} and Lin, {Hsueh Yi} and Tsai, {Tsung Han}",
year = "2012",
doi = "10.1109/ISPACS.2012.6473572",
language = "???core.languages.en_GB???",
isbn = "9781467350815",
series = "ISPACS 2012 - IEEE International Symposium on Intelligent Signal Processing and Communications Systems",
pages = "658--662",
booktitle = "ISPACS 2012 - IEEE International Symposium on Intelligent Signal Processing and Communications Systems",
note = "20th IEEE International Symposium on Intelligent Signal Processing and Communications Systems, ISPACS 2012 ; Conference date: 04-11-2012 Through 07-11-2012",
}