To obtain accurate power estimation, which plays an important role in low power digital CMOS circuit design, a long input sequence is inevitable and it leads to an exhaustive simulation. In this paper, an effective technique is presented, based on a new model designated as the input PST (Power Sensitive Transition) to compact the input sequence. According to this model, the inputs are divided into several bit-groups such that the inputs in a bit-group an with similar PSTIV (PST Importance Value). According to the GIPST (Grouped Input PST) combination, the original input sequence is divided into several subsets with smaller variances. A compact sequence is then generated by randomly sampling from each subset with probability proportional to the subset size. As the experimental results demonstrate, the proposed technique does outperform the conventional compaction method based on the Hamming distance. Especially for the circuits with control inputs, the proposed method can have over 300% reduction in estimation error.