Abstract
This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.
Original language | English |
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Pages (from-to) | 3580-3583 |
Number of pages | 4 |
Journal | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
Volume | E88-A |
Issue number | 12 |
DOIs | |
State | Published - Dec 2005 |
Keywords
- FPGA
- Frequency-scaling
- Low power
- NOC