Frequency-scaling approach for managing power consumption in NOCs

Chun Lung Hsu, Wen Tso Wang, Ying Fu Hong

Research output: Contribution to journalArticlepeer-review

4 Scopus citations


This work presents a frequency-scaling low-power (FSLP) design methodology for managing power consumption of cores in the tile-based network-on-chip (NOC) architecture. A moving picture experts group (MPEG) core is tested using the field-programmable gate array (FPGA) implementation to verify the feasibility of the proposed method. Measurement results show that about 30% power consumption can be saved in the MPEG core and reveal that the proposed FSLP design method can be suitable for cores in the tile-based NOC applications.

Original languageEnglish
Pages (from-to)3580-3583
Number of pages4
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number12
StatePublished - Dec 2005


  • FPGA
  • Frequency-scaling
  • Low power
  • NOC


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