FPGA prototyping for CORDIC-based OFDM baseband receiver

Chih Feng Wu; Muh Tian Shiue

doi:10.1109/EDSSC.2014.7061161

FPGA prototyping for CORDIC-based OFDM baseband receiver

Chih Feng Wu, Muh Tian Shiue

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

1 Scopus citations

Abstract

In this paper, a FPGA prototyping of CORDIC-based OFDM baseband receiver is presented to demonstrate the joint carrier synchronization and channel equalization algorithm. The versatile arithmetics of CORDIC are employed to realize various baseband operations, including gain adjustment, phase compensation, initial gain/phase estimation and derotator. The maximum uncoded data rate of the FPGA prototyping is 72 Mbps for 64-QAM modulation. The measured EVM for given SNR=26 dB and 64-QAM is -31 dB. The physical design shows that the core area is 1.2 mm² with 0.18 μm CMOS technology. The core power consumption is 33.2 mW with 1.8 V supply voltage and 40 MHz operating clock.

Original language	English
Title of host publication	2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479923342
DOIs	https://doi.org/10.1109/EDSSC.2014.7061161
State	Published - 13 Mar 2014
Event	2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014 - Chengdu, China Duration: 18 Jun 2014 → 20 Jun 2014

Publication series

Name	2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014

Conference

Conference	2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014
Country/Territory	China
City	Chengdu
Period	18/06/14 → 20/06/14

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10.1109/EDSSC.2014.7061161

Cite this

Wu, C. F., & Shiue, M. T. (2014). FPGA prototyping for CORDIC-based OFDM baseband receiver. In 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014 Article 7061161 (2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/EDSSC.2014.7061161

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abstract = "In this paper, a FPGA prototyping of CORDIC-based OFDM baseband receiver is presented to demonstrate the joint carrier synchronization and channel equalization algorithm. The versatile arithmetics of CORDIC are employed to realize various baseband operations, including gain adjustment, phase compensation, initial gain/phase estimation and derotator. The maximum uncoded data rate of the FPGA prototyping is 72 Mbps for 64-QAM modulation. The measured EVM for given SNR=26 dB and 64-QAM is -31 dB. The physical design shows that the core area is 1.2 mm2 with 0.18 μm CMOS technology. The core power consumption is 33.2 mW with 1.8 V supply voltage and 40 MHz operating clock.",

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Wu, CF & Shiue, MT 2014, FPGA prototyping for CORDIC-based OFDM baseband receiver. in 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014., 7061161, 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014, Institute of Electrical and Electronics Engineers Inc., 2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014, Chengdu, China, 18/06/14. https://doi.org/10.1109/EDSSC.2014.7061161

FPGA prototyping for CORDIC-based OFDM baseband receiver. / Wu, Chih Feng; Shiue, Muh Tian.
2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 7061161 (2014 IEEE International Conference on Electron Devices and Solid-State Circuits, EDSSC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AB - In this paper, a FPGA prototyping of CORDIC-based OFDM baseband receiver is presented to demonstrate the joint carrier synchronization and channel equalization algorithm. The versatile arithmetics of CORDIC are employed to realize various baseband operations, including gain adjustment, phase compensation, initial gain/phase estimation and derotator. The maximum uncoded data rate of the FPGA prototyping is 72 Mbps for 64-QAM modulation. The measured EVM for given SNR=26 dB and 64-QAM is -31 dB. The physical design shows that the core area is 1.2 mm2 with 0.18 μm CMOS technology. The core power consumption is 33.2 mW with 1.8 V supply voltage and 40 MHz operating clock.

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FPGA prototyping for CORDIC-based OFDM baseband receiver

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