FPGA implementation of FastICA based on floating-point arithmetic design for real-time blind source separation

Kuo Kai Shyu, Ming Huan Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

16 Scopus citations

Abstract

Independent component analysis (ICA) is usually used for blind source separation (BSS), and the FastICA algorithm separates the independent sources from their mixtures by measuring nongaussianity using Kurtosis. In this paper, the field programmable gate array (FPGA) implementation of FastICA for real-time signal process is proposed and the sample rate of 192 kHz is reached under the presented architecture. The floating-point arithmetic design provides better accuracy and higher dynamic performance than fixed-point design for implementation of digital signal processing algorithm. The FPGA design is based on a hierarchical concept, and the experimental results of the design are presented.

Original languageEnglish
Title of host publicationInternational Joint Conference on Neural Networks 2006, IJCNN '06
Pages2785-2792
Number of pages8
StatePublished - 2006
EventInternational Joint Conference on Neural Networks 2006, IJCNN '06 - Vancouver, BC, Canada
Duration: 16 Jul 200621 Jul 2006

Publication series

NameIEEE International Conference on Neural Networks - Conference Proceedings
ISSN (Print)1098-7576

Conference

ConferenceInternational Joint Conference on Neural Networks 2006, IJCNN '06
Country/TerritoryCanada
CityVancouver, BC
Period16/07/0621/07/06

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