FPGA implementation of a high-speed two dimensional discrete wavelet transform

This paper proposes a high-speed VLSI architecture for implementing the forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme which allows its critical path to take only one adder delay is used to increase the clock rate. The proposed design enables 100% hardware use and faster computing than other 2D DWT architectures. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array(FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.