Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

Yeong Kang La; Liang Gee Chen; Tsung Han Tsai; Po Cheng Wu

Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

Yeong Kang La, Liang Gee Chen, Tsung Han Tsai, Po Cheng Wu

Department of Electrical Engineering

Research output: Contribution to conference › Paper › peer-review

3 Scopus citations

Abstract

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

Original language	English
Pages	144-147
Number of pages	4
State	Published - 1997
Event	Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3) - Santa Barbara, CA, USA Duration: 26 Oct 1997 → 29 Oct 1997

Conference

Conference	Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3)
City	Santa Barbara, CA, USA
Period	26/10/97 → 29/10/97

Cite this

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title = "Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation",

abstract = "This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.",

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AU - La, Yeong Kang

AU - Chen, Liang Gee

AU - Tsai, Tsung Han

AU - Wu, Po Cheng

PY - 1997

Y1 - 1997

N2 - This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

AB - This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

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M3 - 會議論文

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SP - 144

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Y2 - 26 October 1997 through 29 October 1997

ER -

Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

Abstract

Conference

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