Abstract
This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.
Original language | English |
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Pages | 144-147 |
Number of pages | 4 |
State | Published - 1997 |
Event | Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3) - Santa Barbara, CA, USA Duration: 26 Oct 1997 → 29 Oct 1997 |
Conference
Conference | Proceedings of the 1997 International Conference on Image Processing. Part 2 (of 3) |
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City | Santa Barbara, CA, USA |
Period | 26/10/97 → 29/10/97 |