Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation

Yeong Kang La, Liang Gee Chen, Tsung Han Tsai, Po Cheng Wu

Research output: Contribution to conferencePaperpeer-review

3 Scopus citations

Abstract

This paper describes a data-interlacing architecture with two-dimensional (2-D) data-reuse for full-search block-matching algorithm. Based on a one-dimensional processing element (PE) array and two data-interlacing shift-register arrays, the proposed architecture can efficiently reuse data to decrease external memory accesses and save the pin counts. It also achieves 100% hardware utilization and a high throughput rate. In addition, the same chips can be cascaded for different block sizes, search ranges, and pixel rates.

Original languageEnglish
Pages144-147
Number of pages4
StatePublished - 1997
EventProceedings of the 1997 International Conference on Image Processing. Part 2 (of 3) - Santa Barbara, CA, USA
Duration: 26 Oct 199729 Oct 1997

Conference

ConferenceProceedings of the 1997 International Conference on Image Processing. Part 2 (of 3)
CitySanta Barbara, CA, USA
Period26/10/9729/10/97

Fingerprint

Dive into the research topics of 'Flexible high-throughput VLSI architecture with 2-D data-reuse for full-search motion estimation'. Together they form a unique fingerprint.

Cite this