FinFET Plus: A scalable FinFET architecture with 3D air-gap and air-spacer toward the 3nm generation and beyond

C. K. Chiang, H. Pai, J. L. Lin, J. K. Chang, M. Y. Lee, E. R. Hsieh, K. S. Li, G. L. Luo, Osbert Cheng, S. S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

A new improvement of FinFET has been demonstrated in the extension of the Moore's Law toward N3 technology and beyond. Instead of conventional STI, the approach is to use air-trench-isolation (ATI) between fins such that, in the width direction, inter-fin spaces with air-gap in the active region become scalable. The scalable ATI FinFET exhibits better DC and RF performance. Results show that the parasitic Cgd reduces 2.3x, and Ion enhances 6.5x; short-channel control is also much better than the conventional ones. Also, along channel direction, air-spacer between gate and S/D has been adopted to further reduce the parasitic capacitance. For a benchmark, in comparison to the conventional FinFET, the propagation delay with 55.8% reduction, active power reduction of 54%, and operating frequency range up to 1.43x gain can be achieved at N3 technology node.

Original languageEnglish
Title of host publicationVLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781665419345
DOIs
StatePublished - 19 Apr 2021
Event2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021 - Hsinchu, Taiwan
Duration: 19 Apr 202122 Apr 2021

Publication series

NameVLSI-TSA 2021 - 2021 International Symposium on VLSI Technology, Systems and Applications, Proceedings

Conference

Conference2021 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA 2021
Country/TerritoryTaiwan
CityHsinchu
Period19/04/2122/04/21

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