Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism

Mu Ying Lee, C. H. Chiu, E. R. Hsieh, G. L. Luo, J. C. Guo, Steve S. Chung

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

A novel low voltage FinFET-based tunneling FET (FinTFET) with face-tunneling mechanism and Ge/SiGe material is proposed in this paper. The proposed device structure enhances the on-state drive current at low Vdd and also provides lower off-state leakage current, steeper sub-threshold slope, higher Ion/Ioff ratio, and smaller parasitic capacitance compared to the other TFETs. These advantages are attributed to a larger tunneling area and proper use of the SiGe-channel, i.e., the suppression of the leakage current, and the channel region with small bandgap Ge which can enhance the tunneling current. Furthermore, a novel hybrid 6T SRAM is proposed and verified to reduce the read disturb and enhance the RSNM/WSNM of SRAM.

Original languageEnglish
Title of host publication2021 Silicon Nanoelectronics Workshop, SNW 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9784863487819
DOIs
StatePublished - 2021
Event26th Silicon Nanoelectronics Workshop, SNW 2021 - Virtual, Online, Japan
Duration: 13 Jun 2021 → …

Publication series

Name2021 Silicon Nanoelectronics Workshop, SNW 2021

Conference

Conference26th Silicon Nanoelectronics Workshop, SNW 2021
Country/TerritoryJapan
CityVirtual, Online
Period13/06/21 → …

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