Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Q. Y. Tong; T. H. Lee; W. J. Kim; T. Y. Tan; U. Goesele; H. M. You; W. Yun; Johnny K.O. Sin

Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Q. Y. Tong, T. H. Lee, W. J. Kim, T. Y. Tan, U. Goesele, H. M. You, W. Yun, Johnny K.O. Sin

Department of Mechanical Engineering

Research output: Contribution to conference › Paper › peer-review

16 Scopus citations

Abstract

The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

Original language	English
Pages	36-37
Number of pages	2
State	Published - 1996
Event	Proceedings of the 1996 IEEE International SOI Conference - Sanibel Island, FL, USA Duration: 30 Sep 1996 → 3 Oct 1996

Conference

Conference	Proceedings of the 1996 IEEE International SOI Conference
City	Sanibel Island, FL, USA
Period	30/09/96 → 3/10/96

Cite this

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title = "Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding",

abstract = "The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.",

author = "Tong, {Q. Y.} and Lee, {T. H.} and Kim, {W. J.} and Tan, {T. Y.} and U. Goesele and You, {H. M.} and W. Yun and Sin, {Johnny K.O.}",

year = "1996",

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pages = "36--37",

note = "Proceedings of the 1996 IEEE International SOI Conference ; Conference date: 30-09-1996 Through 03-10-1996",

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TY - CONF

T1 - Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

AU - Tong, Q. Y.

AU - Lee, T. H.

AU - Kim, W. J.

AU - Tan, T. Y.

AU - Goesele, U.

AU - You, H. M.

AU - Yun, W.

AU - Sin, Johnny K.O.

PY - 1996

Y1 - 1996

N2 - The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

AB - The feasibility of using plasma enhanced chemical vapor deposition TEOS (PETEOS) oxide and associated chemical mechanical polishing (CMP)to form a flat layer on the surface of a processed VLSI bulk Si wafer for direct bonding was evaluated. Results show that the PETEOS oxide can be used to create a very strong bond after annealing at temperatures as low as 300 °C.

UR - http://www.scopus.com/inward/record.url?scp=0030394560&partnerID=8YFLogxK

M3 - 會議論文

AN - SCOPUS:0030394560

SP - 36

EP - 37

T2 - Proceedings of the 1996 IEEE International SOI Conference

Y2 - 30 September 1996 through 3 October 1996

ER -

Feasibility study of VLSI device layer transfer by CMP PETEOS direct bonding

Abstract

Conference

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