Faults analysis on (K+1)-valued PLA structure logic circuits

Hui Min Wang, Chung Len Lee, Jwu E. Chen

Research output: Contribution to journalArticlepeer-review


This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.

Original languageEnglish
Pages (from-to)1001-1010
Number of pages10
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Issue number6
StatePublished - Jun 1993


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