Fault modeling and testing of resistive nonvolatile-8T SRAMs

Yu Ting Li, Yong Xiao Chen, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

3 Scopus citations


In modern system-on-chips (SOCs), static power consumption represents a significant portion of the chip power. Since static random access memory (SRAM) typically occupies more than one half of the chip area, static power of a SOC is mainly constituted by the SRAMs. Resistive nonvolatile-8T (Rnv8T) SRAM has been proposed to alleviate static power and preserve data in power-down mode and provide fast poweron speed. A Rnv8T SRAM cell is composed of a 6T SRAM cell, two resistive devices, and two transistors. In this paper, we define several memristor-related faults for the Rnv8T SRAM considering electrical defects. Also, a March-like test algorithm which can cover simple SRAM faults and defined memristor-related faults are proposed. In comparison with the existing work, the proposed March-like test needs longer test time, but provides better fault coverage on the targeted faults.

Original languageEnglish
Title of host publicationProceedings - 2016 IEEE 34th VLSI Test Symposium, VTS 2016
PublisherIEEE Computer Society
ISBN (Electronic)9781467384544
StatePublished - 23 May 2016
Event34th IEEE VLSI Test Symposium, VTS 2016 - Las Vegas, United States
Duration: 25 Apr 201627 Apr 2016

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference34th IEEE VLSI Test Symposium, VTS 2016
Country/TerritoryUnited States
CityLas Vegas


  • fault model
  • March test
  • Memristor
  • nonvolatile SRAM
  • test algorithm


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