Fault modeling and testing of 1T1R memristor memories

Yong Xiao Chen, Jin Fu Li

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

56 Scopus citations


Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.

Original languageEnglish
Title of host publicationProceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015
PublisherIEEE Computer Society
ISBN (Electronic)9781479975976
StatePublished - 1 Jun 2015
Event2015 33rd IEEE VLSI Test Symposium, VTS 2015 - Napa, United States
Duration: 27 Apr 201529 Apr 2015

Publication series

NameProceedings of the IEEE VLSI Test Symposium


Conference2015 33rd IEEE VLSI Test Symposium, VTS 2015
Country/TerritoryUnited States


  • Non-volatile memory
  • memristor
  • resistive memory
  • test


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