@inproceedings{4d10dec3eeb3428cbdafda2e3b13d276,
title = "Fault modeling and testing of 1T1R memristor memories",
abstract = "Memristor memory has attracted more attentions to act as one of future non-volatile memories. One access transistor and one memristor (1T1R) cell structure can be used to eliminate the issue of sneak path current of memristor memories with crossbar structure. In this paper, we propose several fault models for 1T1R memristor memories based on electrical defects, such as resistive bridge between two nodes, transistor stuck-on and stuck-open faults. In comparison with existing faults, two new faults, write disturbance fault (WDF) and dynamic write disturbance fault (dWDF), are found. In addition, a March test is proposed to cover the defined faults. The March test requires (1+2a+2b)N write operations and 5N read operations for an N-bit memristor memory, where a and b are the number of consecutive Write-1 and Write-0 operations for activating a dWDF.",
keywords = "Non-volatile memory, memristor, resistive memory, test",
author = "Chen, {Yong Xiao} and Li, {Jin Fu}",
note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 2015 33rd IEEE VLSI Test Symposium, VTS 2015 ; Conference date: 27-04-2015 Through 29-04-2015",
year = "2015",
month = jun,
day = "1",
doi = "10.1109/VTS.2015.7116247",
language = "???core.languages.en_GB???",
series = "Proceedings of the IEEE VLSI Test Symposium",
publisher = "IEEE Computer Society",
booktitle = "Proceedings - 2015 IEEE 33rd VLSI Test Symposium, VTS 2015",
}