Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

Meng Shan Wu; Yen Lin Chua; Jin Fu Li; Yun Ting Chuan; Shih Hsu Huang

doi:10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

Meng Shan Wu, Yen Lin Chua, Jin Fu Li, Yun Ting Chuan, Shih Hsu Huang

Department of Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm² using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

Original language	English
Title of host publication	Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350312812
DOIs	https://doi.org/10.1109/ITC-Asia58802.2023.10301173
State	Published - 2023
Event	7th IEEE International Test Conference in Asia, ITC-Asia 2023 - Matsue, Japan Duration: 13 Sep 2023 → 15 Sep 2023

Publication series

Name	Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

Conference

Conference	7th IEEE International Test Conference in Asia, ITC-Asia 2023
Country/Territory	Japan
City	Matsue
Period	13/09/23 → 15/09/23

Keywords

Error Correction Code
STT-MRAM
fault analysis
fault aware
reliability

Access to Document

10.1109/ITC-Asia58802.2023.10301173

運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)
Li, J.-F. (PI)
1/08/25 → 31/07/26
Project: Research

Cite this

Wu, M. S., Chua, Y. L., Li, J. F., Chuan, Y. T., & Huang, S. H. (2023). Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. In Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023 (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ITC-Asia58802.2023.10301173

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abstract = "Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.",

keywords = "Error Correction Code, STT-MRAM, fault analysis, fault aware, reliability",

author = "Wu, {Meng Shan} and Chua, {Yen Lin} and Li, {Jin Fu} and Chuan, {Yun Ting} and Huang, {Shih Hsu}",

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Wu, MS, Chua, YL, Li, JF, Chuan, YT & Huang, SH 2023, Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. in Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023, Institute of Electrical and Electronics Engineers Inc., 7th IEEE International Test Conference in Asia, ITC-Asia 2023, Matsue, Japan, 13/09/23. https://doi.org/10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. / Wu, Meng Shan; Chua, Yen Lin; Li, Jin Fu et al.
Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc., 2023. (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

AU - Wu, Meng Shan

AU - Chua, Yen Lin

AU - Li, Jin Fu

AU - Chuan, Yun Ting

AU - Huang, Shih Hsu

PY - 2023

Y1 - 2023

N2 - Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

AB - Spin-transfer-torque magnetic random access memory (STT-MRAM) has been considered as a candidate for next-generation memory to cope with the scaling challenges of conventional memories. However, the STT-MRAM has the problem of high read failure rate. Effective reliability-enhancement techniques thus are needed for STT-MRAMs. In this paper, we propose a fault-aware error-correction-code (FA-ECC) scheme for STT-MRAMs. The FA-ECC scheme can distinguish a read disturb fault (RDF) from an incorrect read fault (IRF) such that the IRF can be recovered by adjusting the reference resistance to avoid the effect of fault accumulation. Thus, the FA-ECC scheme can be used for concurrent error detection and correction or scrubbing. Analysis results show that the area cost of the FA-ECC scheme is only about 1711μm2 using TSMC 40nm CMOS technology for a STT-MRAM with 64-bit words. Also, the FA-ECC scheme can significantly improve the reliability of STT-MRAM in comparison with a conventional ECC scheme.

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T3 - Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

BT - Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 7th IEEE International Test Conference in Asia, ITC-Asia 2023

Y2 - 13 September 2023 through 15 September 2023

ER -

Wu MS, Chua YL, Li JF, Chuan YT, Huang SH. Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs. In Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023. Institute of Electrical and Electronics Engineers Inc. 2023. (Proceedings - 7th IEEE International Test Conference in Asia, ITC-Asia 2023). doi: 10.1109/ITC-Asia58802.2023.10301173

Fault-Aware ECC Scheme for Enhancing the Read Reliability of STT-MRAMs

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運算記憶體之測試與可靠性增強技術-總計畫暨子計畫一：運算記憶體之測試策略與自動化技術(3/3)

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