Fault-Aware Dependability Enhancement Techniques for Flash Memories

By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fault can be masked. Data shaping (DS) and the page address remapping (PAR) techniques are used to increase the masking probability. DS manipulates the data patterns so that they can be written into the flash pages safely. PAR scrambles the logical-to-physical address mapping for data words and buffer words. Since the effect of a fault is masked for a large proportion of faulty cells, the burden on the error-correction code (ECC) is reduced, as is the number of incorporated redundancies. A novel test-and-repair flow is proposed that uses DS and PAR and corresponding hardware architectures are also developed. A simulator is used to evaluate the hardware overhead, the repair rate, the yield, and the reliability. The experimental results show that these measures are significantly improved with an almost negligible hardware overhead.