@inproceedings{341c26a3d2fa4164bd1a515514272fc5,
title = "Fault analysis on two-level (K + 1)-valued logic circuits",
abstract = "A general form and a set of basic gates in implementing two-level (K + 1)-valued logic circuits are presented. A complete fault analysis on the proposed circuit shows that all fanout stem faults can be collapsed to branch faults. A procedure is derived, based on the fault relationships obtained for fault collapsing. Results show that for a two-level (K + 1)-valued logic circuit, faults can be reduced to 19% of the original total faults.",
author = "Wang, {Hui Min} and Lee, {Chung Len} and Chen, {Jwu E.}",
year = "1992",
month = may,
language = "???core.languages.en_GB???",
isbn = "0818626801",
series = "Proceedings of The International Symposium on Multiple-Valued Logic",
publisher = "Publ by IEEE",
pages = "181--188",
booktitle = "Proceedings of The International Symposium on Multiple-Valued Logic",
note = "Proceedings of the 22nd International Symposium on Multiple-Valued Logic ; Conference date: 27-05-1992 Through 29-05-1992",
}