Fanout fault analysis for digital logic circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen, Beyin Chen

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

Original languageEnglish
Pages (from-to)33-39
Number of pages7
JournalProceedings of the Asian Test Symposium
StatePublished - 1995
EventProceedings of the 1995 4th Asian Test Symposium - Bangalore, India
Duration: 23 Nov 199524 Nov 1995


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