Fanout fault analysis for digital logic circuits

Jwu E. Chen; Chung Len Lee; Wen Zen Shen; Beyin Chen

doi:10.1109/ats.1995.485313

Fanout fault analysis for digital logic circuits

Jwu E. Chen, Chung Len Lee, Wen Zen Shen, Beyin Chen

Department of Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

2 Scopus citations

Abstract

Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

Original language	English
Pages (from-to)	33-39
Number of pages	7
Journal	Proceedings of the Asian Test Symposium
DOIs	https://doi.org/10.1109/ats.1995.485313
State	Published - 1995
Event	Proceedings of the 1995 4th Asian Test Symposium - Bangalore, India Duration: 23 Nov 1995 → 24 Nov 1995

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title = "Fanout fault analysis for digital logic circuits",

abstract = "Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.",

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AU - Chen, Jwu E.

AU - Lee, Chung Len

AU - Shen, Wen Zen

AU - Chen, Beyin

PY - 1995

Y1 - 1995

N2 - Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

AB - Conventional fault relationships are mostly restricted to faults at a gate or within a fanout free region. In this paper, we analyze the fault relationships beyond the fanout free region for general digital logic circuits. An improved fault collapsing procedure is proposed and applied to several kinds of combinational benchmark circuits and 31 sequential benchmark circuits to collapsing faults. Improvements of 2approx.8% for an initial set of target faults of a circuit can be obtained. For some of circuits, the reduction ratio can have up to 20% improvement. This may save a lot of time in test generation and fault simulation processes.

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U2 - 10.1109/ats.1995.485313

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JO - Proceedings of the Asian Test Symposium

JF - Proceedings of the Asian Test Symposium

T2 - Proceedings of the 1995 4th Asian Test Symposium

Y2 - 23 November 1995 through 24 November 1995

ER -

Fanout fault analysis for digital logic circuits

Abstract

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