External capacitorless low dropout linear regulator using cascode structure

Hong Yi Huang, Cheng Yu Chen, Kuo Hsing Cheng

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

2 Scopus citations

Abstract

Recent developments in system-on-chip (SoC) applications lead to an increasing attention on biomedical implantable IC designs. Being implantable, a CMOS low dropout regulator (LDR) with high power supply rejection (PSR) must have an on-chip output capacitor. To achieve a high PSR over a wide frequency range, a cascode technique with power NMOS and power PMOS is utilized to increase the output impedance of the LDR so that the output voltage can be less susceptible to any changes in the input voltage. With this technique, a clean and stable voltage can be produced. The test chip is implemented by TSMC 0.18um 1P6M CMOS technology with an area of 0.872×0.561 mm2. The measured PSR at full load without using large external output capacitor is -33.6 dB at 60MHz and the ripple is 28mV. The power consumption is 2.13 mW and the efficiency is 77%.

Original languageEnglish
Title of host publicationProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
PublisherIEEE Computer Society
Pages236-239
Number of pages4
ISBN (Print)9781467361361
DOIs
StatePublished - 2013
Event2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013 - Karlovy Vary, Czech Republic
Duration: 8 Apr 201310 Apr 2013

Publication series

NameProceedings of the 2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013

Conference

Conference2013 IEEE 16th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2013
Country/TerritoryCzech Republic
CityKarlovy Vary
Period8/04/1310/04/13

Keywords

  • capacitor-free LDO
  • current feedback compensation
  • power supply rejection (PSR)

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